What does : (single colon) do in GNU make files?
How is it different from "="? I don't see any definition for what this specifically does.
See also questions close to this topic
Accessing environment variables from within a recipe in GNU make in windwos
I am trying to set an environment variable in windows and access the same within a recipe windows make. The general code goes something like this:
$(foreach i, $(SHORTCUT_TARGETS), $(eval $(call BUILD_ARTIFACT,$(i),$(param1),$(param2)))) define BUILD_ARTIFACT Rule: Prerequisites @echo Building : $(1) $(if $(filter $(1),string), ,setx LAST $(1) ) $(if $(filter $(1),string),\ @echo path-%LAST%,\ @echo path-$(1) endef
When I run this, the setx command is executed successfully, generally giving an output "SUCCESS: Specified value was saved." But the output of the echo will be path-%LAST% as opposed to an output with the environment variable replaced in. I have tried it from cmd and powershell and I've gotten the same output in both cases. I have also tried replacing setx with set and export, neither approaches produced a positive result.
Why is make complaining "Nothing to be done for 'clean' "?
maketo remove all files except the source files and the make rule file (i.e. the file named
makefile), so I added a phony rule at the end of my
.PHONY:clean clean: $(shell ls | grep -v "[.][ch]" | grep -v makefile | xargs rm)
This does what I intend. But
make: Nothing to be done for 'clean'.
After I run
make clean. Why does this message appear? And how can I make it disappear?
I've been using the following makefile for my C++ projects for several years now. I originally found it online, can't remember where though unfortunately.
It takes all source and header files located in the folder
./srcand places the objects in an
./obj-folder and places the executable binary in
CXX = g++ CXXFLAGS = -std=c++11 -W LDFLAGS = DEPFLAGS = -MM SRC_DIR = ./src OBJ_DIR = ./obj SRC_EXT = .cpp OBJ_EXT = .o TARGET = main SRCS := $(wildcard $(SRC_DIR)/*$(SRC_EXT)) OBJS := $(SRCS:$(SRC_DIR)/%$(SRC_EXT)=$(OBJ_DIR)/%$(OBJ_EXT)) DEP = depend.main .PHONY: clean all depend all: $(TARGET) $(TARGET): $(OBJS) @echo "-> linking $@" @$(CXX) $^ $(LDFLAGS) -o $@ $(OBJ_DIR)/%$(OBJ_EXT) : $(SRC_DIR)/%$(SRC_EXT) @echo "-> compiling $@" @$(CXX) $(CXXFLAGS) -o $@ -c $< clean: @echo "removing objects and main file" @rm -f $(OBJS) $(TARGET) *.out $(SRC_DIR)/%.$(SRC_EXT): $(CXX) $(DEPFLAGS) -MT \ "$(subst $(SRC_DIR),$(OBJ_DIR),$(subst $(SRC_EXT),$(OBJ_EXT),$@))" \ $(addprefix ,$@) >> $(DEP); clear_dependencies: @echo "-> (re-)building dependencies"; @$(RM) $(DEP) depend: clear_dependencies $(SRCS) -include $(DEP)
I am not experienced enough with
maketo evaluate if this Makefile needs to be updated and/or improved. I'd be happy to hear if you have any comments/feedback that can improve it.